1. Field of the Invention
The present invention relates to a technique of controlling a power factor correction circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a power factor correction circuit according to a first related art. This power factor correction circuit is with a current-critical, step-up DC/DC converter.
In FIG. 1, a first rectifier RC1 rectifies and converts an AC voltage of an AC power source Vin into a DC voltage. An output of the first rectifier RC1 is connected to a series circuit including a first winding N1 of a step-up transformer T1, a switching element Q1 made of an n-type MOSFET, and a resistor R5. A series circuit of the switching element Q1 and resistor R5 is connected in parallel with a rectifying-smoothing circuit including a second rectifier D1 and a smoothing capacitor C1. Both ends of the first rectifier RC1 are connected to a series circuit of resistors R1 and R2. Both ends of the smoothing capacitor C1 are connected to a series circuit of resistors R3 and R4.
The series circuit of resistors R1 and R2 forms an input voltage detector detecting an output voltage from the first rectifier RC1 according to a divided voltage provided by the resistors R1 and R2 and outputting a divided input voltage signal Vvin to a multiplier 17.
A controller 100 controls an ON/OFF operation of the switching element Q1 and includes an error amplifier 14, the multiplier 17, comparators CMP3 and CMP4, and a flip-flop FF2.
The error amplifier 14 amplifies an error between a reference voltage Vref (not illustrated) and a divided voltage signal that is obtained by dividing a voltage across the smoothing capacitor C1 by the resistors R3 and R4. The error amplifier 14 outputs the amplified error as an amplified error signal Vcmp to the multiplier 17. The multiplier 17 multiplies the divided input voltage signal Vvin by the amplified error signal Vcmp and outputs the product to an inverting input terminal (as depicted by “−”) of the comparator CMP3.
The resistor R5 acts as a current detector to detect a current passing through the switching element Q1. The comparator CMP3 compares the current Vid detected by the resistor R5 with the product of “Vvin×Vcmp” from the multiplier 17. A result of the comparison from the comparator CMP3 is supplied to a reset terminal of the flip-flop FF2 and the flip-flop FF2 determines an ON period of the switching element Q1.
FIG. 2 illustrates a control operation carried out by the first related art of FIG. 1. An ON period of the switching element Q1 is a period in which the current signal Vid detected by the resistor R5 increases from zero to the product of “Vcmp×Vvin” where Vcmp is the amplified error signal and Vvin is the divided input voltage signal.
The comparator CMP4 compares a voltage of a second winding N2 of the step-up transformer T1 with a reference voltage E1. A result of the comparison is supplied to a set terminal S of the flip-flop FF2. A period in which the voltage of the second winding N2 of the step-up transformer T1 is high defines an OFF period of the switching element Q1.
FIG. 3 illustrates a converter according to a second related art disclosed in U.S. Pat. No. 6,448,745. In the converter, an input voltage U1 is divided by resistors Z11 and Z12 to provide a divided input voltage. An output voltage Uc is divided by resistors Z41 and Z42 to provide a divided output voltage. The divided input voltage, the divided output voltage, and a reference voltage 202 are converted into digital signals by an A/D converter 203. Just after an occurrence of a zero-current state, a digital controller 204 restarts charging a cumulative inductor according to the digitally converted divided input voltage and divided output voltage and an ON time of a shunt switch S.
The digital controller 204 minutely adjusts a pulse width for the shunt switch S, thereby minutely adjusting energy that is conducted according to a result of comparison between an output voltage Uc and a reference voltage.